Semiconductor device fabrication is the process used to create the integrated circuits (ICs) that are present in everyday electrical and electronic devices, and involves a multiple-step sequence of photolithographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material (typically monocrystalline silicon). Modern integrated circuits are produced using, e.g., CMOS production flows (standardized processing sequences) including over 300 sequenced processing steps that are generally divided into Front-end-of-line (front-end) processes and Back-end-of-line (back-end) processes. Front end processing typically involves implanting dopants in the silicon wafer and depositing materials on the substrate that collectively form individual device components (e.g., transistors, capacitors, resistors, etc.). For example, front end processing for a non-volatile memory (NVM) transistor typically involves implanting n-type and p-type dopants into the silicon wafer to form source and drain doped diffusion regions that are disposed in electrically isolated well regions, forming gate oxides and field oxides on the silicon wafer surface, forming polycrystalline silicon (polysilicon) gate structures on the gate oxides, and forming a pre-metal dielectric (“D1” passivation) layer over the polycrystalline gate structures. Back end processing is the second portion of IC fabrication that involves forming a metallization structure including multiple (typically three to eight) metallization layers disposed in a stack, where each metallization layer includes a patterned metal (e.g., aluminum) “wire” layer and an interlevel dielectric (ILD) layer that serves to electrically isolate the patterned metal wires from the subsequently formed patterned metal wires of the next sequential metallization layer in the stack. The patterned metal wires of the various metallization layers interconnect the individual device components by way of metal “via” structures that are formed in conjunction with a contact etch process and extend through the pre-metal dielectric layer and previously formed ILD layers. The last (uppermost) patterned metal layer is covered by a final “topside stack” insulating material layer that is patterned by way of a “pad etch” process to make appropriate connections to the underlying IC, typically by way of connections to the uppermost patterned metal structure).
The ILD and topside stack are typically formed using one or more of Undoped silicate glass (USG), Fluorosilicate glass (FSG) and Borophosphosilicate glass (BPSG). A principal component of USG, FSG and BPSG is silicon dioxide (SiO2), which is commonly used as dielectric material in semiconductor processing, where USG is essentially “pure” SiO2, FSG is essentially SiO2 containing fluorine, and BPSG is SiO2 including both boron and phosphorous. Silicon dioxide (SiO2) and silicon nitride (Si3N4, referred to as SiN for brevity herein) are the two prevalent dielectric material used in semiconductor processing. However, since the dielectric constant of silicon dioxide, which is about 3.9, is lower than that of silicon nitride, which is about 7.5, silicon dioxide is usually preferred for use as an insulation material between active regions or conductive lines, such the patterned metal layer found in back-end metallization structures. Two prevalent reactive gases used for forming silicon dioxide by chemical vapor deposition (CVD), which is commonly used in semiconductor processing, are silicon hydride (silane, SiH4) and tetra-ethyl-ortho-silicate, (TEOS, Si(OC2H5)4). Because the step coverage (gap filling) ability of SiO2 formed using TEOS (referred to herein as “TEOS-based oxide”) is better than SiO2 formed using silane (referred to herein as “silane oxide”), TEOS-based oxide is preferred in semiconductor manufacture. TEOS and ozone (O3) are sometimes used together as reactive gases in an atmospheric-pressure chemical vapor deposition (APCVD) for depositing USG to form shallow trench isolation (STI), inter-poly dielectrics (IPD) or cap layers on inter-level dielectric (ILD) layers in back-end structures.
The importance of hydrogen for the performance of CMOS devices is well known in semiconductor industry. A certain amount of hydrogen at the Silicon-Gate Oxide interface is needed to passivate the surface states (by forming Si—H complexes with dangling bonds). At the same time, excess amounts of hydrogen are responsible for device instabilities. For example, excess hydrogen may result in floating gate memory retention loss (e.g., hydrogen ions discharging single polycrystalline silicon (“single-Poly”) floating gate memories; see U.S. Pat. No. 6,130,172, “Radiation hardened dielectric for EEPROM”, R. Fuller et. al., which teaches that higher radiation hardness of BPSG with lower amounts of hydrogen was associated with lower amount of hole traps associated with hydrogen complexes). Briefly, a problem with semiconductor devices including NVM cells (i.e., erasable and programmable read only memories (EPROM), flash memories, and electrically erasable programmable read only memories (EEPROMs)) that are fabricated using conventional semiconductor fabrication techniques is that front-end NVM structures (specifically the floating gates) may be detrimentally affected by hydrogen ions that are generated during the back-end process, and then migrate/diffuse toward the front-end structures, especially at high temperatures, where the act to reduce the amount of charge that can be stored on the floating gate structures. Hydrogen atoms are also known to interact with the bulk silicon defects created by ionizing radiation. For example, N. Shlopak, et. al. Physica Status Solidi, Volume 137, Issue 1, pages 165-171, 1993, teaches that preliminary treatment of silicon in hydrogen plasma leads to a significant increase in radiation hardening. It was assumed that passivation of deep radiation defects occurred due to radiation activated hydrogen originating from inactive hydrogen containing species. Thus, the necessity to control the generation and migration of hydrogen atoms/ions and other ions generated during back-end processing is well known in the industry.
An early approach to controlling the generation/migration of hydrogen generated during back-end processing is to form a gettering/barrier layer on the pre-metal dielectric layer that serves to protect the underlying transistors and other IC elements before beginning back-end processing. Typical gettering materials include phosphosilicate glass (PSG) and BPSG. In addition, a layer of silicon nitride or silicon oxy-nitride is typically formed under the PSG or BPSG that serves as an etch stop during contact etch, and also contributes to the performance of the gettering/barrier layer. However, a problem with the gettering/barrier layer solution is that mobile hydrogen atoms are known to penetrate the gettering/barrier layer and diffuse to the floating gate of NVM devices, thus reducing floating gate storage capacity and causing reduced device operating parameters.
In order to prevent mobile atoms from affecting characteristics of the MOS transistors or memory cells, Mehta et al. (U.S. Pat. No. 6,071,784) provides a method of annealing the silicon nitride (SiN) layer and silicon oxy-nitride layer so as to eliminate charge loss from non-volatile memory devices. This approach involves forming a barrier layer or an etch stop layer that covers the MOS device/FG structure, and then high temperature annealing at 750° C. is used to remove mobile atoms from the barrier layer or the etch stop layer. An additional dielectric layer is then formed on the barrier layer or the etch stop layer to protect the dehydrated barrier layer from moisture re-absorption. However, a disadvantage of this process is the addition of an extra high-temperature annealing process during the semiconductor fabrication process (especially in embedded processes) because the additional thermal budget alters the characteristics of semiconductor elements. In addition, this process does not account for the possibility that mobile hydrogen atoms and mobile ions may be re-adsorbed into the barrier layer, or may migrate/diffuse to the semiconductor elements under the barrier layer through the contact holes.
Tseng et al. (US. Pat. Application 20030003658) addresses some of the shortcoming mentioned above by providing a fabrication method for NVM devices that involes effectively preventing diffusion of the mobile ions or the hydrogen atoms into the memory device barrier by forming a spacer on the sidewall of the contact hole. This solution, however, has a disadvantage in that it adds a large number of process steps to the process flow, which greatly increases overall IC fabrication costs. In addition, the effect of the additional spacers on the reliability of the contact is questionable. Further, other penetration paths for hydrogen atoms/ions (e.g., diffusion through the gettering/barrier layer) are not addressed by this solution.
Additional proposed solutions to minimizing hydrogen atom/ion migration damage include methodologies for decreasing the amount of hydrogen or moisture contained in back-side materials, thus minimizing hydrogen atom/ion generation during back-side processing. One approach utilizes a “reflow” bake to achieve “silane oxide” protection quality using a modified “TEOS-based oxide” in BPSG formation, but this approach cannot be used in CMOS process flows involving Salicide formation, and adds a high thermal budget. Other proposed solutions require too many additional steps to be added to a typical CMOS process flow (i.e., the resulting added cost and possible effect on the CMOS platform are major drawbacks), and the retention improvement is considered by the inventors to be unsatisfactory. Other proposed solutions claim charge retention improvement from the use of optimized SiN etch stop layers, but the present inventors determined that even optimized SiN adds another source of H+ ions, and even a “perfect” optimized SiN etch stop layer would not sufficiently curtail the generation/migration of back-end-generated ions. Other solutions propose improving the quality of the TEOS-based oxide used to form the first interlayer dielectric (ILD-1) by adding a gettering/barrier layer (e.g., BPSG, SiN, etc.), but the present inventors determined that these solutions have limited effectiveness because the H+ ions source is not limited to the ILD-1 layer, but rather related to the ILD layers of every metallization layer of the metallization structure stack. In summary, based on extensive research, the present inventors concluded none of the prior art solutions mentioned above serve to adequately reduce or eliminate the migration of back-end-generated hydrogen atoms/ions into front-end structures (e.g., polysilicon structures or doped diffusion regions), particularly H+ ions generated by back-end processing involving aluminum interactions with residual moisture disposed in ILD layers.
What is needed is a modified back-end processing methodology and modified back-end metallization structure that suppresses both the creation and migration of mobile hydrogen atoms/ions, thus improving a semiconductor device's operating performance (e.g., improving data retention in the NVM cells).